;	P16C84.INC
;	MPASM header for PIC16C84
;	Rev. A - Johan Bodin 1996
;	Rev. B - Johan Bodin 1996 - __EEBASE__ constant added.
;	Rev. C - Johan Bodin 1996 - General cleanup...

	NOLIST

	IFNDEF	__16C84
	  MESSG "Selected processor does not match header file P16C84.INC"
	ENDIF


;	Destination symbols

W	EQU	0
w	EQU	0
F	EQU	1
f	EQU	1
file	EQU	1
File	EQU	1
FILE	EQU	1
itself	EQU	1
Itself	EQU	1
ITSELF	EQU	1


;	Register files

INDF	EQU	0x00
TMR0	EQU	0x01
PCL	EQU	0x02
STATUS	EQU	0x03
FSR	EQU	0x04
PORTA	EQU	0x05
PORTB	EQU	0x06
EEDATA	EQU	0x08
EEADR	EQU	0x09
PCLATH	EQU	0x0A
INTCON	EQU	0x0B
OPTI	EQU	0x81
TRISA	EQU	0x85
TRISB	EQU	0x86
EECON1	EQU	0x88
EECON2	EQU	0x89


;	STATUS register bits

B_IRP	EQU	7
B_RP1	EQU	6
B_RP0	EQU	5
B_NTO	EQU	4
B_NPD	EQU	3
B_Z	EQU	2
B_DC	EQU	1
B_C	EQU	0


;	Complete bit addresses for bit write/test on STATUS

#define	_IRP	STATUS,B_IRP
#define	_RP1	STATUS,B_RP1
#define	_RP0	STATUS,B_RP0
#define	_NTO	STATUS,B_NTO
#define	_NPD	STATUS,B_NPD
#define	_Z	STATUS,B_Z
#define	_DC	STATUS,B_DC
#define	_C	STATUS,B_C


;	INTCON register bits

B_GIE	EQU	7
B_EEIE	EQU	6
B_T0IE	EQU	5
B_INTE	EQU	4
B_RBIE	EQU	3
B_T0IF	EQU	2
B_INTF	EQU	1
B_RBIF	EQU	0


;	Complete bit addresses for bit write/test on INTCON

#define	_GIE	INTCON,B_GIE
#define	_EEIE	INTCON,B_EEIE
#define	_T0IE	INTCON,B_T0IE
#define	_INTE	INTCON,B_INTE
#define	_RBIE	INTCON,B_RBIE
#define	_T0IF	INTCON,B_T0IF
#define	_INTF	INTCON,B_INTF
#define	_RBIF	INTCON,B_RBIF


;	OPTION register bits

B_NRBPU	EQU	7
B_INTED	EQU	6
B_T0CS	EQU	5
B_T0SE	EQU	4
B_PSA	EQU	3
B_PS2	EQU	2
B_PS1	EQU	1
B_PS0	EQU	0


;	Complete bit addresses for bit write/test on OPTION

#define	_NRBPU	OPTI,B_NRBPU
#define	_INTED	OPTI,B_INTED
#define	_T0CS	OPTI,B_T0CS
#define	_T0SE	OPTI,B_T0SE
#define	_PSA	OPTI,B_PSA
#define	_PS2	OPTI,B_PS2
#define	_PS1	OPTI,B_PS1
#define	_PS0	OPTI,B_PS0


;	EECON1 register bits

B_EEIF	EQU	4
B_WRERR	EQU	3
B_WREN	EQU	2
B_WR	EQU	1
B_RD	EQU	0


;	Complete bit addresses for bit write/test on EECON1

#define	_EEIF	EECON1,B_EEIF
#define	_WRERR	EECON1,B_WRERR
#define	_WREN	EECON1,B_WREN
#define	_WR	EECON1,B_WR
#define	_RD	EECON1,B_RD


;	RAM Definition

	__MAXRAM	0xAF
	__BADRAM	0x07, 0x30-0x7F, 0x87


;	Configuration Bits, one from each group should be &-ed together

; Code protection

_CP_ON		EQU	0x3FEF
_CP_OFF		EQU	0x3FFF

; Power-up timer

_PWRTE_ON	EQU	0x3FFF
_PWRTE_OFF	EQU	0x3FF7

; Watchdog timer

_WDT_ON		EQU	0x3FFF
_WDT_OFF	EQU	0x3FFB

; Oscillator type

_LP_OSC		EQU	0x3FFC
_XT_OSC		EQU	0x3FFD
_HS_OSC		EQU	0x3FFE
_RC_OSC		EQU	0x3FFF


;	Pseudo base adddress for the EEPROM (for hex file embedded data)

__EEBASE__	EQU	0x2100

	LIST